1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device with improved source diffused regions, which is applied to, for example, a PROM (Programmable Read Only Memory) or an EEPROM (Electrically Erasable and Programmable ROM), and a manufacturing method thereof.
2. Description of the Related Art
For example, PROMs, which allow the stored data to be erased by ultraviolet rays, and EEPROMs, which allow the stored data to be erased electrically, are capable of retaining the stored data almost indefinitely. Because these memories enable the stored data to be erased or rewritten, they have been used widely as firmware for a system where the modification of programs is expected, a system where a program is constructed, taking into account compatibility with other systems, or a system for allowing the positive change of program specifications. Especially, flash EEPROMs capable of erasing the stored data in unison are widely used as program memorizes for microcomputers.
FIG. 13 is a sectional view of a conventional flash EEPROM. A first gate insulating film 4 is formed on a semiconductor substrate 1 made of, for example, p-type polysilicon. On the first gate insulating film 4, a floating gate 5 made of, for example, polysilicon is formed. On the floating gate 5 is formed a second gate insulating film 6, on which a control gate 7 made of, for example, polysilicon is formed to complete a floating-gate transistor. The control gate 7 constitutes a word line. A multilayer structure of the floating gate 5 and control gate 7 is covered with a thermal oxide film 8, on which an interlayer insulating film 9 of, for example, SiO.sub.2 is deposited. In the semiconductor substrate 1 between the multilayer gate structures, n-type impurities are diffused so as to form source regions 2 and drain regions 3 one after another alternately. A contact hole 16 is made in the interlayer insulating film 9. In the contact hole 16, the drain region 3 is exposed. After this, a wire 10 is formed of metal, such as Al, on the interlayer insulating film 9 to provide a bit line. The wire 10 is connected to the drain region through the contact hole 16. On the wire 10, a passivation film 11, such as a PSG (Phosphor Silicate Glass) film, is deposited.
FIG. 14 is a NOR nonvolatile semiconductor memory where memory cells of the above-described structure are arranged in a matrix. In FIG. 14, the same parts as those in FIG. 13 are indicated by the same reference characters. The drain 3 of each memory cell is connected to bit lines B0, B1, B2, and B3, respectively. The sources 2 of the individual memory cells are grounded via each common source line 21. Each control gate 7 is connected to word lines W0, W1, and W3, respectively.
Referring to FIG. 15, the operation of the flash EEPROM will be explained. In FIG. 15, the same parts as those in FIG. 13 are shown by the same reference characters.
To write data in a memory cell, electrons are injected into the floating gate 5. First, a high voltage of approximately 7 V is also applied to a drain electrode D at the same time that a high voltage of approximately 12.0 V is applied to a gate electrode G connected to the control gate 7. By biasing the memory cell this way, some of electrons accelerated in the pinch-off region near the drain 3 act as hot electrons, which are captured at the floating gate 5. The saturation amount of captured electrons is determined by the potential of the floating gate 5. When electrons are captured by the floating gate 5, the threshold voltage Vth of the transistor controlled by the control gate 7 rises. The presence and absence of a change in the threshold voltage are caused to correspond to 1 level and 0 level, respectively.
To read the stored data from the memory cell, approximately 1.5 V is applied to drain electrode D at the same time that a voltage of approximately 5 V is applied to gate electrode G. Because the voltage of gate electrode G is as low as 5 V, hot electrons will not be injected into the floating gate 5. The transistor whose floating gate 5 is not injected with electrons turns on, allowing a read current to flow. The transistor whose floating gate 5 is injected with electrons remains off, because its threshold voltage Vth stays high.
To erase the stored data from the memory cell, the electrons in the floating gate 5 are forced to discharge into the source 2. In this case, for example, 0 V is applied to gate electrode G and a high voltage ranging from 11 V to 13 V is applied to source electrode S. At this time, when the potential difference between the floating gate 5 and source electrode S enhances the electric field applied to the first gate insulating film 4, the electrons in the floating gate 5 are discharged into the source 2 in the form of tunnel current.
As shown in FIG. 16, in a conventional nonvolatile semiconductor memory, an element-isolating field oxide film 12 is formed so as to make a curve at the boundary between itself and the source region 2 or the drain region 3. If the gates 5 and 7 are deviated to the right or the left in the figure from the proper place, the width W between transistors constituting the memory cell varies. Further, the field oxide film 12 has a region 13 projecting from gates 5 and 7 into the source region 2, which sets a limit to making the structure much finer.
To overcome this limitation, as the elements in semiconductor devices are becoming much finer, a self-aligned (SAS: Self Aligned Source) method making use of a gate in forming a source region 2 is being used more. When the SAS method is used, the source of a memory cell is formed with respect to the gate in a self-aligning manner, with the result that there is no gap between the source/drain region and the gate. Furthermore, because the field oxide film does not project into the source region, it is possible to make the elements finer.
FIG. 17 shows a case where a source region is formed on the semiconductor substrate 1 by the SAS method. As described above, the gates 5 and 7 of a memory cell are formed on the semiconductor substrate 1. After this, a photoresist 14 is coated over a portion of the gate 7 and a portion in which a drain region 3 is to be formed. Then, the field oxide film 12 in the portion which is to be the common source line 12 is removed by RIE (Reactive Ion Etching) (hereinafter, anisotropic etching on an oxide film is referred to as oxide-film RIE). At this time, because on the semiconductor substrate 1, the portion scheduled to be the source region 2 in the portion scheduled to be the common source line 21 on which the field oxide film 12 is not formed, is not coated with the photoresist 14, this portion is etched by the oxide film RIE. As a result, the portion in which the source region is to be formed is dug a little. Thus, when an EEPROM cell is completed, the surface of the source region 2 is lower than the surface of the semiconductor substrate 1 under the floating gate 5 of the memory cell and the first insulating gate 4, as shown in FIG. 13.
In an EEPROM cell with a common source line, when the surface of the source region 2 is lower than the surface of the semiconductor substrate under the floating gate 5 and the first gate insulating film 4 and steps are formed at the boundary between the two surfaces, the strength of an electric field varies at the step portions. Because of this, when in the flash EEPROM, the data is erased by causing electrons to discharge from an end of the floating gate 5 into the source region 2, the erasing cannot be effected sometimes, making it difficult to erase the data stably.